RSRC LVINLBVW: ltP <@R/'Bq0]m`LLُ B~0ُ B~'(° bzX XpmrG5 +LVINstate_machine_30Jan2008.vi VIXN SimDog.xnodePTH0N Simulation ScriptingCompanion Diagram SimConfigNode SimDog.xnode̷VICC SimParams.ctlPTH0O Simulation ScriptingCompanion Diagram SimConfigNode SimParams.ctl/@ Initial Time (s)@ Final Time (s)@ Step Size (s)o_simSolvers.ctl@ Runge-Kutta 1 (Euler) Runge-Kutta 2 Runge-Kutta 3 Runge-Kutta 4Runge-Kutta 23 (variable)Runge-Kutta 45 (variable)BDF (variable)Adams-Moulton (variable)Rosenbrock (variable)Discrete States Only Linearizer State Query Trim Eval ODE Solver@ Minimum Step Size (s)@ Maximum Step Size (s)@ Relative Tolerance@ Absolute Tolerance@!Software Timing@ Initial Step Size (s) @!Automatic Fixed Step Size?"@!Automatic Discrete Step Size?@ Discrete Step Size (s)@!Calculate using Time Step@! Solver Wired?@Prev.Frm.Expected End@Prev.Frm.Actual End@!Prev.Frm.Finished Late?@Prev.Iter.Expected End@Prev.Iter.Actual End@!Prev.Iter.Finished Late?@Expected Iteration Start@Actual Iteration Start@Expected Frame Start@Actual Frame Start@0 Source Name@0Name @Period@Deadline @Offset @Start@Priority @Timeout@ No Change/Process missed periods, maintain original phase/Discard missed periods, maintain original phase-Process missed periods, ignore original phase-Discard missed periods, ignore original phaseModed@NormalAbortedAsynchronous wakeupTiming source errorTimed loop errorTimeout Wakeup reason @!status @code@0source@P#$%Error@0 Source Type@0Secondary Source Type@Global End Time@Global Start Time@!Full Solver Reset:SIMSCR Execution Mode.ctl@Execution Mode@! Nan/Inf Check~ SimParams.ctlh@P+  !"&'()*+,-Timing.SIMUSIMMPVICC_simSolvers.ctlPTH0Q Simulation ScriptingCompanion Diagram SimConfigNode_simSolvers.ctlo_simSolvers.ctl@ Runge-Kutta 1 (Euler) Runge-Kutta 2 Runge-Kutta 3 Runge-Kutta 4Runge-Kutta 23 (variable)Runge-Kutta 45 (variable)BDF (variable)Adams-Moulton (variable)Rosenbrock (variable)Discrete States Only Linearizer State Query Trim Eval Solver MethodSIMUSIMMPVICCSIMSCR Execution Mode.ctlPTH0G SimulationImplementationSharedSIMSCR Execution Mode.ctl:SIMSCR Execution Mode.ctl@Execution ModeSIMUSIMM VIVI_simCreateTimingSource.viPTH0[ Simulation ScriptingCompanion Diagram SimConfigNode_simCreateTimingSource.vi2@ Initial Time (s)@ Final Time (s)@ Step Size (s)@ Runge-Kutta 1 (Euler) Runge-Kutta 2 Runge-Kutta 3 Runge-Kutta 4Runge-Kutta 23 (variable)Runge-Kutta 45 (variable)BDF (variable)Adams-Moulton (variable)Rosenbrock (variable)Discrete States Only Linearizer State Query Trim Eval ODE Solver@ Minimum Step Size (s)@ Maximum Step Size (s)@ Relative Tolerance@ Absolute Tolerance@!Software Timing@ Initial Step Size (s) @!Automatic Fixed Step Size?"@!Automatic Discrete Step Size?@ Discrete Step Size (s)@!Calculate using Time Step@! Solver Wired?@Prev.Frm.Expected End@Prev.Frm.Actual End@!Prev.Frm.Finished Late?@Prev.Iter.Expected End@Prev.Iter.Actual End@!Prev.Iter.Finished Late?@Expected Iteration Start@Actual Iteration Start@Expected Frame Start@Actual Frame Start@0 Source Name@0Name @Period@Deadline @Offset @Start@Priority @Timeout@ No Change/Process missed periods, maintain original phase/Discard missed periods, maintain original phase-Process missed periods, ignore original phase-Discard missed periods, ignore original phaseModed@NormalAbortedAsynchronous wakeupTiming source errorTimed loop errorTimeout Wakeup reason @!status @code@0source@P$%&Error@0 Source Type@0Secondary Source Type@Global End Time@Global Start Time@!Full Solver Reset@Execution Mode@! Nan/Inf Checkj@P+  !"#'()*+,-. timing (out)h@P+  !"#'()*+,-. timing (in)< /0x 1SIMUSIMMPVIVISIM Unbundle Sim Info.viPTH0F SimulationImplementationSharedSIM Unbundle Sim Info.vi2@ Initial Time (s)@ Final Time (s)@ Step Size (s)o_simSolvers.ctl@ Runge-Kutta 1 (Euler) Runge-Kutta 2 Runge-Kutta 3 Runge-Kutta 4Runge-Kutta 23 (variable)Runge-Kutta 45 (variable)BDF (variable)Adams-Moulton (variable)Rosenbrock (variable)Discrete States Only Linearizer State Query Trim Eval ODE Solver@ Minimum Step Size (s)@ Maximum Step Size (s)@ Relative Tolerance@ Absolute Tolerance@!Software Timing@ Initial Step Size (s) @!Automatic Fixed Step Size?"@!Automatic Discrete Step Size?@ Discrete Step Size (s)@!Calculate using Time Step@! Solver Wired?@Prev.Frm.Expected End@Prev.Frm.Actual End@!Prev.Frm.Finished Late?@Prev.Iter.Expected End@Prev.Iter.Actual End@!Prev.Iter.Finished Late?@Expected Iteration Start@Actual Iteration Start@Expected Frame Start@Actual Frame Start@0 Source Name@0Name @Period@Deadline @Offset @Start@Priority @Timeout@ No Change/Process missed periods, maintain original phase/Discard missed periods, maintain original phase-Process missed periods, ignore original phase-Discard missed periods, ignore original phaseModed@NormalAbortedAsynchronous wakeupTiming source errorTimed loop errorTimeout Wakeup reason @!status @code@0source@P#$%Error@0 Source Type@0Secondary Source Type@Global End Time@Global Start Time@!Full Solver Reset:SIMSCR Execution Mode.ctl@Execution Mode@! Nan/Inf Check SimParams.ctlv@P+  !"&'()*+,-SimulationParameters SimParams.ctlz@P+  !"&'()*+,-SimulationParameters OutL.//&/////0/  1SIMUSIMMPVIXNXDataNode.xnodePTH09platform TimedLoop XDataNodeXDataNode.xnodeVICCXDNodeRunTimeDep.lvlibtiming_clust.ctlPTH0:Platform TimedLoop XDataNodetiming_clust.ctl @Expected End [f-1]@Actual End [f-1]@!Finished Late? [f-1]@Expected End [i-1]@Actual End [i-1]@!Finished Late? [i-1]@Expected Start [i]@Actual Start [i]@Expected Start [f]@Actual Start [f]@0 Source Name@0Name @Period@Deadline @Offset @Start@Priority @TimeoutXDNodeRunTimeDep.lvlibnitl_modes.ctl@ No Change/Process missed periods, maintain original phase/Discard missed periods, maintain original phase-Process missed periods, ignore original phase-Discard missed periods, ignore original phaseModeXDNodeRunTimeDep.lvlib wakeup.ctl~@NormalAbortedAsynchronous wakeupTiming source errorTimed loop errorTimeout Wakeup Reason @!status @code@0source@PError@0 Source Type@0Secondary Source Type@Global End Time@Global Start Time@Frame Duration@Iteration Duration@ Assigned CPUzcsXDNodeRunTimeDep.lvlibtiming_clust.ctl`@P TimingVICCXDNodeRunTimeDep.lvlibnitl_modes.ctlPTH08Platform TimedLoop XDataNodenitl_modes.ctlXDNodeRunTimeDep.lvlibnitl_modes.ctl@ No Change/Process missed periods, maintain original phase/Discard missed periods, maintain original phase-Process missed periods, ignore original phase-Discard missed periods, ignore original phaseModeVICCXDNodeRunTimeDep.lvlib wakeup.ctlPTH04Platform TimedLoop XDataNode wakeup.ctlXDNodeRunTimeDep.lvlib wakeup.ctl~@NormalAbortedAsynchronous wakeupTiming source errorTimed loop errorTimeout Wakeup reasonVIVIXDNodeRunTimeDep.lvlibloadlvalarms.viPTH09Platform TimedLoop XDataNodeloadlvalarms.viVIVISIM Init From Cluster.viPTH0F SimulationImplementationSharedSIM Init From Cluster.viSIM integration method.ctl@ RK 1 (Euler) Linearizer State Query Trim EvalAdamsRK 3RK 4RK 45BDFRK 2RK 23 RosenbrockDiscrete States Onlycontinuous integrator@ initial time@ final time@ step size@ proposed step size@ max step size@ min step size@ discrete time step@ max step ratioeSIM diagram eval stage.ctlA@Init Minor Substep Major SubstepFinalDiag Eval Stage@ Substep Index@ Timestep Index@ simulation time@ current timestep base@ proposed step time@ absolute tolerance@ relative tolerance@!step accepted?@!step complete? @!Halt?@!reset integrator?@ machine epsilon@ min float @!status @code@0source@Perror@ Method Order@!Finished Late [i-1]@!Discrete step?@!NaN and Inf check?@ Final Timestep Index@!(maj+disc)or(init)?@!Full Solver Reset:SIMSCR Execution Mode.ctl@Execution Mode@!check vector sizes?@!solver handles zc?@ Current Idx @0Tag@@' Node Tags@ Input Width @Disc ID@ Num Cont St@ Cont St Idx@ Num Disc St@ Disc St Idx@ Output WidthI2RZSIM Registry Node Header.ctl#@P)*+,-./ Node Header@@0 Node Headers @ Signal@@2 Node Data@@2 Node Outputs@@2 Z.C. SignalsQSIM trigger type.ctl3@risingfallingeithernone trigger type @@6Z.C. Trigger TypesC:SIM Registry Node Record.ctl@P3457 Node Record@@8 Node Data @ Numeric@@:inputs@@:outputs@@:reset@@: lower limits@@: upper limitsGSIM limit type.ctl+@upperlowerbothnone limit type@@@ limit types@@6 reset types @@:initial conditions@@: reset I.C. @!Boolean@@Elimited?@0String@@G State NamesRSIM solver state data.ctl0@P ;<=>?ABCDFHCont State data@ tick period (sec)@ time (ticks)@@Efire?@ period (sec)@@M period (sec)@@M skew (sec)@ period (sec)@@P period (tick)@@P skew (tick)@PNOQRregistry@!discrete blocks?@ steps per tick@ steps to tick@!discrete tick?FcASIM discrete data.ctl(@PJKLSTUVW DiscreteInfo@@: Disc StatesBSIM Discrete state data.ctl@PYHDisc State data@Error Block IDH2Q!SIM Simulation Registry Error.ctl@P[Registry Error @Numeric@@] ZC IndicesTlWSIM Simulation Registry.ctl0@P &(19IXZ\^Simulation Registry@!variable step solver?@!First Substep?@!Continuous States?nSIM simulation data.ctlj@P&  !"#$%_`abSimulation data out@ Initial Time (s)@ Final Time (s)@ Step Size (s)o_simSolvers.ctl@ Runge-Kutta 1 (Euler) Runge-Kutta 2 Runge-Kutta 3 Runge-Kutta 4Runge-Kutta 23 (variable)Runge-Kutta 45 (variable)BDF (variable)Adams-Moulton (variable)Rosenbrock (variable)Discrete States Only Linearizer State Query Trim Eval ODE Solver@ Minimum Step Size (s)@ Maximum Step Size (s)@ Relative Tolerance@ Absolute Tolerance@!Software Timing@ Initial Step Size (s) @!Automatic Fixed Step Size?"@!Automatic Discrete Step Size?@ Discrete Step Size (s)@!Calculate using Time Step@! Solver Wired?@Prev.Frm.Expected End@Prev.Frm.Actual End@!Prev.Frm.Finished Late?@Prev.Iter.Expected End@Prev.Iter.Actual End@!Prev.Iter.Finished Late?@Expected Iteration Start@Actual Iteration Start@Expected Frame Start@Actual Frame Start@0 Source Name@0Name @Period@Deadline @Offset @Start@Priority @Timeout@ No Change/Process missed periods, maintain original phase/Discard missed periods, maintain original phase-Process missed periods, ignore original phase-Discard missed periods, ignore original phaseModed@NormalAbortedAsynchronous wakeupTiming source errorTimed loop errorTimeout Wakeup reason@PError@0 Source Type@0Secondary Source Type@Global End Time@Global Start Time@! Nan/Inf Check SimParams.ctlz@P+defghijklmnopqrstuvwxyz{|}~"#SimulationParameters out SimParams.ctlv@P+defghijklmnopqrstuvwxyz{|}~"#SimulationParameters,c` SIMUSIMMPVICCSIM limit type.ctlPTH0@ SimulationImplementationSharedSIM limit type.ctlGSIM limit type.ctl+@upperlowerbothnone limit typeSIMUSIMM VICCSIM trigger type.ctlPTH0B SimulationImplementationSharedSIM trigger type.ctlQSIM trigger type.ctl3@risingfallingeithernone trigger typeSIMUSIMM VIXNSIMX Summation.xnodePTH0L SimulationSignalArithmeticSIMX SummationSIMX Summation.xnode̺&VIXNSIMX Multiplication.xnodePTH0V SimulationSignalArithmeticSIMX MultiplicationSIMX Multiplication.xnodeVIVI&SIM Integrator distributor (scalar).viPTH0q simulationContinuousLinearImplementationSIM Integrator.llb&SIM Integrator distributor (scalar).vimSIM integration method.ctl@ RK 1 (Euler) Linearizer State Query Trim EvalAdamsRK 3RK 4RK 45BDFRK 2RK 23 RosenbrockDiscrete States Onlycontinuous integrator@ initial time@ final time@ step size@ proposed step size@ max step size@ min step size@ discrete time step@ max step ratioeSIM diagram eval stage.ctlA@Init Minor Substep Major SubstepFinalDiag Eval Stage@ Substep Index@ Timestep Index@ simulation time@ current timestep base@ proposed step time@ absolute tolerance@ relative tolerance@!step accepted?@!step complete? @!Halt?@!reset integrator?@ machine epsilon@ min float @!status @code@0source@Perror@ Method Order@!Finished Late [i-1]@!Discrete step?@!NaN and Inf check?@ Final Timestep Index@!(maj+disc)or(init)?@!Full Solver Reset:SIMSCR Execution Mode.ctl@Execution Mode@!check vector sizes?@!solver handles zc?@ Current Idx @0Tag@@& Node Tags@ Input Width @Disc ID@ Num Cont St@ Cont St Idx@ Num Disc St@ Disc St Idx@ Output WidthI2RZSIM Registry Node Header.ctl#@P()*+,-. Node Header@@/ Node Headers @ Signal@@1 Node Data@@1 Node Outputs@@1 Z.C. SignalsQSIM trigger type.ctl3@risingfallingeithernone trigger type @@5Z.C. Trigger TypesC:SIM Registry Node Record.ctl@P2346 Node Record@@7 Node Data @ Numeric@@9inputs@@9outputs@@9reset@@9 lower limits@@9 upper limitsGSIM limit type.ctl+@upperlowerbothnone limit type@@? limit types@@5 reset types @@9initial conditions@@9 reset I.C. @!Boolean@@Dlimited?@0String@@F State NamesRSIM solver state data.ctl0@P :;<=>@ABCEGCont State data@ tick period (sec)@ time (ticks)@@Dfire?@ period (sec)@@L period (sec)@@L skew (sec)@ period (sec)@@O period (tick)@@O skew (tick)@PMNPQregistry@!discrete blocks?@ steps per tick@ steps to tick@!discrete tick?FcASIM discrete data.ctl(@PIJKRSTUV DiscreteInfo@@9 Disc StatesBSIM Discrete state data.ctl@PXGDisc State data@Error Block IDH2Q!SIM Simulation Registry Error.ctl@PZRegistry Error @Numeric@@\ ZC IndicesTlWSIM Simulation Registry.ctl0@P %'08HWY[]Simulation Registry@!variable step solver?@!First Substep?@!Continuous States?nSIM simulation data.ctlf@P&  !"#$^_`aSimulation data@ upper limitnSIM simulation data.ctlj@P&  !"#$^_`aSimulation data out @ output@ initial condition@!limited?@ lower limit"@0DNL_Simulation CallChain@ Block Idx OutLb?cdedddfghddijk  lSIMUSIMMPVIXNSIMX Halt.xnodePTH09 SimulationUtility SIMX HaltSIMX Halt.xnode̺VIVI sim halt.viPTH0: simulationutilityimplementation sim halt.vif @!Halt?SIM integration method.ctl@ RK 1 (Euler) Linearizer State Query Trim EvalAdamsRK 3RK 4RK 45BDFRK 2RK 23 RosenbrockDiscrete States Onlycontinuous integrator@ initial time@ final time@ step size@ proposed step size@ max step size@ min step size@ discrete time step@ max step ratioeSIM diagram eval stage.ctlA@Init Minor Substep Major SubstepFinalDiag Eval Stage@ Substep Index@ Timestep Index@ simulation time@ current timestep base@ proposed step time@ absolute tolerance@ relative tolerance@!step accepted?@!step complete?@!reset integrator?@ machine epsilon@ min float @!status @code@0source@Perror@ Method Order@!Finished Late [i-1]@!Discrete step?@!NaN and Inf check?@ Final Timestep Index@!(maj+disc)or(init)?@!Full Solver Reset:SIMSCR Execution Mode.ctl@Execution Mode@!check vector sizes?@!solver handles zc?@ Current Idx @0Tag@@' Node Tags@ Input Width @Disc ID@ Num Cont St@ Cont St Idx@ Num Disc St@ Disc St Idx@ Output WidthI2RZSIM Registry Node Header.ctl#@P)*+,-./ Node Header@@0 Node Headers @ Signal@@2 Node Data@@2 Node Outputs@@2 Z.C. SignalsQSIM trigger type.ctl3@risingfallingeithernone trigger type @@6Z.C. Trigger TypesC:SIM Registry Node Record.ctl@P3457 Node Record@@8 Node Data @ Numeric@@:inputs@@:outputs@@:reset@@: lower limits@@: upper limitsGSIM limit type.ctl+@upperlowerbothnone limit type@@@ limit types@@6 reset types @@:initial conditions@@: reset I.C. @!Boolean@@Elimited?@0String@@G State NamesRSIM solver state data.ctl0@P ;<=>?ABCDFHCont State data@ tick period (sec)@ time (ticks)@@Efire?@ period (sec)@@M period (sec)@@M skew (sec)@ period (sec)@@P period (tick)@@P skew (tick)@PNOQRregistry@!discrete blocks?@ steps per tick@ steps to tick@!discrete tick?FcASIM discrete data.ctl(@PJKLSTUVW DiscreteInfo@@: Disc StatesBSIM Discrete state data.ctl@PYHDisc State data@Error Block IDH2Q!SIM Simulation Registry Error.ctl@P[Registry Error @Numeric@@] ZC IndicesTlWSIM Simulation Registry.ctl0@P &(19IXZ\^Simulation Registry@!variable step solver?@!First Substep?@!Continuous States?nSIM simulation data.ctlf@P&  !"#$%_`abSimulation datanSIM simulation data.ctlj@P&  !"#$%_`abSimulation data outLcd eSIMUSIMMPVIXNSIMX TimeWaveform.xnodePTH0O Simulation SignalDisplaySIMX TimeWaveformSIMX TimeWaveform.xnode̺VIVISIM Time Waveform (scalar).viPTH0h Simulation SignalDisplayImplementationSIM Time Waveform.llbSIM Time Waveform (scalar).vih @ ValueSIM integration method.ctl@ RK 1 (Euler) Linearizer State Query Trim EvalAdamsRK 3RK 4RK 45BDFRK 2RK 23 RosenbrockDiscrete States Onlycontinuous integrator@ initial time@ final time@ step size@ proposed step size@ max step size@ min step size@ discrete time step@ max step ratioeSIM diagram eval stage.ctlA@Init Minor Substep Major SubstepFinalDiag Eval Stage@ Substep Index@ Timestep Index@ simulation time@ current timestep base@ proposed step time@ absolute tolerance@ relative tolerance@!step accepted?@!step complete? @!Halt?@!reset integrator?@ machine epsilon@ min float @!status @code@0source@Perror@ Method Order@!Finished Late [i-1]@!Discrete step?@!NaN and Inf check?@ Final Timestep Index@!(maj+disc)or(init)?@!Full Solver Reset:SIMSCR Execution Mode.ctl@Execution Mode@!check vector sizes?@!solver handles zc?@ Current Idx @0Tag@@( Node Tags@ Input Width @Disc ID@ Num Cont St@ Cont St Idx@ Num Disc St@ Disc St Idx@ Output WidthI2RZSIM Registry Node Header.ctl#@P*+,-./0 Node Header@@1 Node Headers @ Signal@@3 Node Data@@3 Node Outputs@@3 Z.C. SignalsQSIM trigger type.ctl3@risingfallingeithernone trigger type @@7Z.C. Trigger TypesC:SIM Registry Node Record.ctl@P4568 Node Record@@9 Node Data @ Numeric@@;inputs@@;outputs@@;reset@@; lower limits@@; upper limitsGSIM limit type.ctl+@upperlowerbothnone limit type@@A limit types@@7 reset types @@;initial conditions@@; reset I.C. @!Boolean@@Flimited?@0String@@H State NamesRSIM solver state data.ctl0@P <=>?@BCDEGICont State data@ tick period (sec)@ time (ticks)@@Ffire?@ period (sec)@@N period (sec)@@N skew (sec)@ period (sec)@@Q period (tick)@@Q skew (tick)@POPRSregistry@!discrete blocks?@ steps per tick@ steps to tick@!discrete tick?FcASIM discrete data.ctl(@PKLMTUVWX DiscreteInfo@@; Disc StatesBSIM Discrete state data.ctl@PZIDisc State data@Error Block IDH2Q!SIM Simulation Registry Error.ctl@P\Registry Error @Numeric@@^ ZC IndicesTlWSIM Simulation Registry.ctl0@P ')2:JY[]_Simulation Registry@!variable step solver?@!First Substep?@!Continuous States?nSIM simulation data.ctlf@P&  !"#$%&`abcSimulation data@TWaveform ChartnSIM simulation data.ctlj@P&  !"#$%&`abcSimulation data out4 def gSIMUSIMMPVIVI$SIM Integrator collector (scalar).viPTH0o simulationContinuousLinearImplementationSIM Integrator.llb$SIM Integrator collector (scalar).vinSIM integration method.ctl@ RK 1 (Euler) Linearizer State Query Trim EvalAdamsRK 3RK 4RK 45BDFRK 2RK 23 RosenbrockDiscrete States Onlycontinuous integrator@ initial time@ final time@ step size@ proposed step size@ max step size@ min step size@ discrete time step@ max step ratioeSIM diagram eval stage.ctlA@Init Minor Substep Major SubstepFinalDiag Eval Stage@ Substep Index@ Timestep Index@ simulation time@ current timestep base@ proposed step time@ absolute tolerance@ relative tolerance@!step accepted?@!step complete? @!Halt?@!reset integrator?@ machine epsilon@ min float @!status @code@0source@Perror@ Method Order@!Finished Late [i-1]@!Discrete step?@!NaN and Inf check?@ Final Timestep Index@!(maj+disc)or(init)?@!Full Solver Reset:SIMSCR Execution Mode.ctl@Execution Mode@!check vector sizes?@!solver handles zc?@ Current Idx @0Tag@@& Node Tags@ Input Width @Disc ID@ Num Cont St@ Cont St Idx@ Num Disc St@ Disc St Idx@ Output WidthI2RZSIM Registry Node Header.ctl#@P()*+,-. Node Header@@/ Node Headers @ Signal@@1 Node Data@@1 Node Outputs@@1 Z.C. SignalsQSIM trigger type.ctl3@risingfallingeithernone trigger type @@5Z.C. Trigger TypesC:SIM Registry Node Record.ctl@P2346 Node Record@@7 Node Data @ Numeric@@9inputs@@9outputs@@9reset@@9 lower limits@@9 upper limitsGSIM limit type.ctl+@upperlowerbothnone limit type@@? limit types@@5 reset types @@9initial conditions@@9 reset I.C. @!Boolean@@Dlimited?@0String@@F State NamesRSIM solver state data.ctl0@P :;<=>@ABCEGCont State data@ tick period (sec)@ time (ticks)@@Dfire?@ period (sec)@@L period (sec)@@L skew (sec)@ period (sec)@@O period (tick)@@O skew (tick)@PMNPQregistry@!discrete blocks?@ steps per tick@ steps to tick@!discrete tick?FcASIM discrete data.ctl(@PIJKRSTUV DiscreteInfo@@9 Disc StatesBSIM Discrete state data.ctl@PXGDisc State data@Error Block IDH2Q!SIM Simulation Registry Error.ctl@PZRegistry Error @Numeric@@\ ZC IndicesTlWSIM Simulation Registry.ctl0@P %'08HWY[]Simulation Registry@!variable step solver?@!First Substep?@!Continuous States?nSIM simulation data.ctlf@P&  !"#$^_`aSimulation dataOSIM trigger type.ctl1@risingfallingeithernone reset type@ upper limit@ Block Idx InnSIM simulation data.ctlj@P&  !"#$^_`aSimulation data out @ input @ initial condition for reset @ reset@ lower limit"@0DNL_Simulation CallChainLbcdefgghgigj?klg  mSIMUSIMMPVIXNSIMX Manager.xnodePTH0M SimulationImplementationShared SIMX ManagerSIMX Manager.xnode̷VIVISIM fixed stepsize manager.viPTH0K SimulationImplementationSharedSIM fixed stepsize manager.vif@!step complete?SIM integration method.ctl@ RK 1 (Euler) Linearizer State Query Trim EvalAdamsRK 3RK 4RK 45BDFRK 2RK 23 RosenbrockDiscrete States Onlycontinuous integrator@ initial time@ final time@ step size@ proposed step size@ max step size@ min step size@ discrete time step@ max step ratioeSIM diagram eval stage.ctlA@Init Minor Substep Major SubstepFinalDiag Eval Stage@ Substep Index@ Timestep Index@ simulation time@ current timestep base@ proposed step time@ absolute tolerance@ relative tolerance@!step accepted? @!Halt?@!reset integrator?@ machine epsilon@ min float @!status @code@0source@Perror@ Method Order@!Finished Late [i-1]@!Discrete step?@!NaN and Inf check?@ Final Timestep Index@!(maj+disc)or(init)?@!Full Solver Reset:SIMSCR Execution Mode.ctl@Execution Mode@!check vector sizes?@!solver handles zc?@ Current Idx @0Tag@@& Node Tags@ Input Width @Disc ID@ Num Cont St@ Cont St Idx@ Num Disc St@ Disc St Idx@ Output WidthI2RZSIM Registry Node Header.ctl#@P()*+,-. Node Header@@/ Node Headers @ Signal@@1 Node Data@@1 Node Outputs@@1 Z.C. SignalsQSIM trigger type.ctl3@risingfallingeithernone trigger type @@5Z.C. Trigger TypesC:SIM Registry Node Record.ctl@P2346 Node Record@@7 Node Data @ Numeric@@9inputs@@9outputs@@9reset@@9 lower limits@@9 upper limitsGSIM limit type.ctl+@upperlowerbothnone limit type@@? limit types@@5 reset types @@9initial conditions@@9 reset I.C. @!Boolean@@Dlimited?@0String@@F State NamesRSIM solver state data.ctl0@P :;<=>@ABCEGCont State data@ tick period (sec)@ time (ticks)@@Dfire?@ period (sec)@@L period (sec)@@L skew (sec)@ period (sec)@@O period (tick)@@O skew (tick)@PMNPQregistry@!discrete blocks?@ steps per tick@ steps to tick@!discrete tick?FcASIM discrete data.ctl(@PIJKRSTUV DiscreteInfo@@9 Disc StatesBSIM Discrete state data.ctl@PXGDisc State data@Error Block IDH2Q!SIM Simulation Registry Error.ctl@PZRegistry Error @Numeric@@\ ZC IndicesTlWSIM Simulation Registry.ctl0@P %'08HWY[]Simulation Registry@!variable step solver?@!First Substep?@!Continuous States?nSIM simulation data.ctlj@P&  !"#$^_`aSimulation data outnSIM simulation data.ctlf@P&  !"#$^_`aSimulation databcd(  eSIMUSIMMPVIVISIM Linearizer manager.viPTH0{ SimulationContinuousLinearImplementationSharedSolversSIM Linearizer Manager.llbSIM Linearizer manager.vig @!Stop?SIM integration method.ctl@ RK 1 (Euler) Linearizer State Query Trim EvalAdamsRK 3RK 4RK 45BDFRK 2RK 23 RosenbrockDiscrete States Onlycontinuous integrator@ initial time@ final time@ step size@ proposed step size@ max step size@ min step size@ discrete time step@ max step ratioeSIM diagram eval stage.ctlA@Init Minor Substep Major SubstepFinalDiag Eval Stage@ Substep Index@ Timestep Index@ simulation time@ current timestep base@ proposed step time@ absolute tolerance@ relative tolerance@!step accepted?@!step complete? @!Halt?@!reset integrator?@ machine epsilon@ min float @!status @code@0source@Perror@ Method Order@!Finished Late [i-1]@!Discrete step?@!NaN and Inf check?@ Final Timestep Index@!(maj+disc)or(init)?@!Full Solver Reset:SIMSCR Execution Mode.ctl@Execution Mode@!check vector sizes?@!solver handles zc?@ Current Idx @0Tag@@' Node Tags@ Input Width @Disc ID@ Num Cont St@ Cont St Idx@ Num Disc St@ Disc St Idx@ Output WidthI2RZSIM Registry Node Header.ctl#@P)*+,-./ Node Header@@0 Node Headers @ Signal@@2 Node Data@@2 Node Outputs@@2 Z.C. SignalsQSIM trigger type.ctl3@risingfallingeithernone trigger type @@6Z.C. Trigger TypesC:SIM Registry Node Record.ctl@P3457 Node Record@@8 Node Data @ Numeric@@:inputs@@:outputs@@:reset@@: lower limits@@: upper limitsGSIM limit type.ctl+@upperlowerbothnone limit type@@@ limit types@@6 reset types @@:initial conditions@@: reset I.C. @!Boolean@@Elimited?@0String@@G State NamesRSIM solver state data.ctl0@P ;<=>?ABCDFHCont State data@ tick period (sec)@ time (ticks)@@Efire?@ period (sec)@@M period (sec)@@M skew (sec)@ period (sec)@@P period (tick)@@P skew (tick)@PNOQRregistry@!discrete blocks?@ steps per tick@ steps to tick@!discrete tick?FcASIM discrete data.ctl(@PJKLSTUVW DiscreteInfo@@: Disc StatesBSIM Discrete state data.ctl@PYHDisc State data@Error Block IDH2Q!SIM Simulation Registry Error.ctl@P[Registry Error @Numeric@@] ZC IndicesTlWSIM Simulation Registry.ctl0@P &(19IXZ\^Simulation Registry@!variable step solver?@!First Substep?@!Continuous States?nSIM simulation data.ctlj@P&  !"#$%_`abSimulation data outnSIM simulation data.ctlf@P&  !"#$%_`abSimulation datacde( fSIMUSIMMPVIVISIM Trim manager.viPTH0o SimulationContinuousLinearImplementationSharedSolversSIM Trim Manager.llbSIM Trim manager.vig @!Stop?SIM integration method.ctl@ RK 1 (Euler) Linearizer State Query Trim EvalAdamsRK 3RK 4RK 45BDFRK 2RK 23 RosenbrockDiscrete States Onlycontinuous integrator@ initial time@ final time@ step size@ proposed step size@ max step size@ min step size@ discrete time step@ max step ratioeSIM diagram eval stage.ctlA@Init Minor Substep Major SubstepFinalDiag Eval Stage@ Substep Index@ Timestep Index@ simulation time@ current timestep base@ proposed step time@ absolute tolerance@ relative tolerance@!step accepted?@!step complete? @!Halt?@!reset integrator?@ machine epsilon@ min float @!status @code@0source@Perror@ Method Order@!Finished Late [i-1]@!Discrete step?@!NaN and Inf check?@ Final Timestep Index@!(maj+disc)or(init)?@!Full Solver Reset:SIMSCR Execution Mode.ctl@Execution Mode@!check vector sizes?@!solver handles zc?@ Current Idx @0Tag@@' Node Tags@ Input Width @Disc ID@ Num Cont St@ Cont St Idx@ Num Disc St@ Disc St Idx@ Output WidthI2RZSIM Registry Node Header.ctl#@P)*+,-./ Node Header@@0 Node Headers @ Signal@@2 Node Data@@2 Node Outputs@@2 Z.C. SignalsQSIM trigger type.ctl3@risingfallingeithernone trigger type @@6Z.C. Trigger TypesC:SIM Registry Node Record.ctl@P3457 Node Record@@8 Node Data @ Numeric@@:inputs@@:outputs@@:reset@@: lower limits@@: upper limitsGSIM limit type.ctl+@upperlowerbothnone limit type@@@ limit types@@6 reset types @@:initial conditions@@: reset I.C. @!Boolean@@Elimited?@0String@@G State NamesRSIM solver state data.ctl0@P ;<=>?ABCDFHCont State data@ tick period (sec)@ time (ticks)@@Efire?@ period (sec)@@M period (sec)@@M skew (sec)@ period (sec)@@P period (tick)@@P skew (tick)@PNOQRregistry@!discrete blocks?@ steps per tick@ steps to tick@!discrete tick?FcASIM discrete data.ctl(@PJKLSTUVW DiscreteInfo@@: Disc StatesBSIM Discrete state data.ctl@PYHDisc State data@Error Block IDH2Q!SIM Simulation Registry Error.ctl@P[Registry Error @Numeric@@] ZC IndicesTlWSIM Simulation Registry.ctl0@P &(19IXZ\^Simulation Registry@!variable step solver?@!First Substep?@!Continuous States?nSIM simulation data.ctlj@P&  !"#$%_`abSimulation data outnSIM simulation data.ctlj@P&  !"#$%_`abSimulation data incde( fSIMUSIMMPVIVISIM TrimLin Global Error.viPTH0d SimulationModel Trim and LinearizeSIM Lin Trim Shared.llbSIM TrimLin Global Error.vi @!status @code@0source@P error outPSIMUSIMMPVIVISIM stop conditions.viPTH0D SimulationImplementationSharedSIM stop conditions.vih @!resultSIM integration method.ctl@ RK 1 (Euler) Linearizer State Query Trim EvalAdamsRK 3RK 4RK 45BDFRK 2RK 23 RosenbrockDiscrete States Onlycontinuous integrator@ initial time@ final time@ step size@ proposed step size@ max step size@ min step size@ discrete time step@ max step ratioeSIM diagram eval stage.ctlA@Init Minor Substep Major SubstepFinalDiag Eval Stage@ Substep Index@ Timestep Index@ simulation time@ current timestep base@ proposed step time@ absolute tolerance@ relative tolerance@!step accepted?@!step complete? @!Halt?@!reset integrator?@ machine epsilon@ min float @!status @code@0source@Perror@ Method Order@!Finished Late [i-1]@!Discrete step?@!NaN and Inf check?@ Final Timestep Index@!(maj+disc)or(init)?@!Full Solver Reset:SIMSCR Execution Mode.ctl@Execution Mode@!check vector sizes?@!solver handles zc?@ Current Idx @0Tag@@( Node Tags@ Input Width @Disc ID@ Num Cont St@ Cont St Idx@ Num Disc St@ Disc St Idx@ Output WidthI2RZSIM Registry Node Header.ctl#@P*+,-./0 Node Header@@1 Node Headers @ Signal@@3 Node Data@@3 Node Outputs@@3 Z.C. SignalsQSIM trigger type.ctl3@risingfallingeithernone trigger type @@7Z.C. Trigger TypesC:SIM Registry Node Record.ctl@P4568 Node Record@@9 Node Data @ Numeric@@;inputs@@;outputs@@;reset@@; lower limits@@; upper limitsGSIM limit type.ctl+@upperlowerbothnone limit type@@A limit types@@7 reset types @@;initial conditions@@; reset I.C. @!Boolean@@Flimited?@0String@@H State NamesRSIM solver state data.ctl0@P <=>?@BCDEGICont State data@ tick period (sec)@ time (ticks)@@Ffire?@ period (sec)@@N period (sec)@@N skew (sec)@ period (sec)@@Q period (tick)@@Q skew (tick)@POPRSregistry@!discrete blocks?@ steps per tick@ steps to tick@!discrete tick?FcASIM discrete data.ctl(@PKLMTUVWX DiscreteInfo@@; Disc StatesBSIM Discrete state data.ctl@PZIDisc State data@Error Block IDH2Q!SIM Simulation Registry Error.ctl@P\Registry Error @Numeric@@^ ZC IndicesTlWSIM Simulation Registry.ctl0@P ')2:JY[]_Simulation Registry@!variable step solver?@!First Substep?@!Continuous States?nSIM simulation data.ctlj@P&  !"#$%&`abcSimulation data Out"@Default Collector Stop ModenSIM simulation data.ctlf@P&  !"#$%&`abcSimulation data,def`  gSIMUSIMMPVIVISIMSCR Append VI info.viPTH0L Simulation ScriptingCompanion DiagramSIMSCR Append VI info.vi @!status @code@0source@P error out@Perror in SIMUSIMMPVIVISIM MergeSimErrors.viPTH0C SimulationImplementationSharedSIM MergeSimErrors.vi @!status @code@0source@P error out@Perror 2@Perror 1,` SIMUSIMMPVIVISIM Bundle Sim Info.viPTH0D SimulationImplementationSharedSIM Bundle Sim Info.vi3@ Initial Time (s)@ Final Time (s)@ Step Size (s)o_simSolvers.ctl@ Runge-Kutta 1 (Euler) Runge-Kutta 2 Runge-Kutta 3 Runge-Kutta 4Runge-Kutta 23 (variable)Runge-Kutta 45 (variable)BDF (variable)Adams-Moulton (variable)Rosenbrock (variable)Discrete States Only Linearizer State Query Trim Eval ODE Solver@ Minimum Step Size (s)@ Maximum Step Size (s)@ Relative Tolerance@ Absolute Tolerance@!Software Timing@ Initial Step Size (s) @!Automatic Fixed Step Size?"@!Automatic Discrete Step Size?@ Discrete Step Size (s)@!Calculate using Time Step@! Solver Wired?@Prev.Frm.Expected End@Prev.Frm.Actual End@!Prev.Frm.Finished Late?@Prev.Iter.Expected End@Prev.Iter.Actual End@!Prev.Iter.Finished Late?@Expected Iteration Start@Actual Iteration Start@Expected Frame Start@Actual Frame Start@0 Source Name@0Name @Period@Deadline @Offset @Start@Priority @Timeout@ No Change/Process missed periods, maintain original phase/Discard missed periods, maintain original phase-Process missed periods, ignore original phase-Discard missed periods, ignore original phaseModed@NormalAbortedAsynchronous wakeupTiming source errorTimed loop errorTimeout Wakeup reason @!status @code@0source@P$%&Error@0 Source Type@0Secondary Source Type@Global End Time@Global Start Time@!Full Solver Reset:SIMSCR Execution Mode.ctl@Execution Mode@! Nan/Inf Check SimParams.ctlv@P+  !"#'()*+,-.Simulation Params out@P$%&error in SimParams.ctlv@P+  !"#'()*+,-.Simulation Params in< /01x  2SIMUSIMMPVIVI_simClearTimingSource.viPTH0Z Simulation ScriptingCompanion Diagram SimConfigNode_simClearTimingSource.vi1@ Initial Time (s)@ Final Time (s)@ Step Size (s)o_simSolvers.ctl@ Runge-Kutta 1 (Euler) Runge-Kutta 2 Runge-Kutta 3 Runge-Kutta 4Runge-Kutta 23 (variable)Runge-Kutta 45 (variable)BDF (variable)Adams-Moulton (variable)Rosenbrock (variable)Discrete States Only Linearizer State Query Trim Eval ODE Solver@ Minimum Step Size (s)@ Maximum Step Size (s)@ Relative Tolerance@ Absolute Tolerance@!Software Timing@ Initial Step Size (s) @!Automatic Fixed Step Size?"@!Automatic Discrete Step Size?@ Discrete Step Size (s)@!Calculate using Time Step@! Solver Wired?@Prev.Frm.Expected End@Prev.Frm.Actual End@!Prev.Frm.Finished Late?@Prev.Iter.Expected End@Prev.Iter.Actual End@!Prev.Iter.Finished Late?@Expected Iteration Start@Actual Iteration Start@Expected Frame Start@Actual Frame Start@0 Source Name@0Name @Period@Deadline @Offset @Start@Priority @Timeout@ No Change/Process missed periods, maintain original phase/Discard missed periods, maintain original phase-Process missed periods, ignore original phase-Discard missed periods, ignore original phaseModed@NormalAbortedAsynchronous wakeupTiming source errorTimed loop errorTimeout Wakeup reason @!status @code@0source@P$%&Error@0 Source Type@0Secondary Source Type@Global End Time@Global Start Time@!Full Solver Reset:SIMSCR Execution Mode.ctl@Execution Mode@! Nan/Inf Check~ SimParams.ctlh@P+  !"#'()*+,-.Timing4 /0SIMUSIMMPHq c d1` P c@flg@oRt@eof@Pudf @!stop@!dfd@!txd@!old@!extP  P c; @ h0 [m]@ dfd@ txd@ old@ extP  c4@ F_in_on [m3/s]P @ F_in_offP @ F_out_offP @ F_out_on [m3/s]P 0 P## @%*P""#####$&''### @(! @6P''*++'$'##''####,##- @. @$3 P111 @2P,,,, P$, @5 P-,( @7P$,,, @9P####P ##''##;## @<&P)/03/4068:=T @?P@PA##'A @PCCC5PCCC9 P' @F*P######''G c8@TWaveform Chart @Tdfd @Ttxd @Told @TextP JKLMN c3 @ h [m]P Q@ h_max [m]P S c(@!Valve_inP V  c/@! Valve_outP Y  @ A [m2]P [ @!Pause?P ] @ h_min [m]P _ P c@This_state_is_now_active:@dfd@txd@old@extP cdefg c,@!Switch_filling?P j P- @lP'$$ P- @o P @qPmnppr$@ Initial Time (s)@ Final Time (s)@ Step Size (s)o_simSolvers.ctl@ Runge-Kutta 1 (Euler) Runge-Kutta 2 Runge-Kutta 3 Runge-Kutta 4Runge-Kutta 23 (variable)Runge-Kutta 45 (variable)BDF (variable)Adams-Moulton (variable)Rosenbrock (variable)Discrete States Only Linearizer State Query Trim Eval ODE Solver@ Minimum Step Size (s)@ Maximum Step Size (s)@ Relative Tolerance@ Absolute Tolerance@!Software Timing@ Initial Step Size (s) @!Automatic Fixed Step Size?"@!Automatic Discrete Step Size?@ Discrete Step Size (s)@!Calculate using Time Step@! Solver Wired?@Prev.Frm.Expected End@Prev.Frm.Actual End@!Prev.Frm.Finished Late?@Prev.Iter.Expected End@Prev.Iter.Actual End@!Prev.Iter.Finished Late?@Expected Iteration Start@Actual Iteration Start@Expected Frame Start@Actual Frame Start@0 Source Name@0Name @Period@Deadline @Offset @Start@Priority @Timeout@ No Change/Process missed periods, maintain original phase/Discard missed periods, maintain original phase-Process missed periods, ignore original phase-Discard missed periods, ignore original phaseModed@NormalAbortedAsynchronous wakeupTiming source errorTimed loop errorTimeout Wakeup reason @!status @code@0source@PError@0 Source Type@0Secondary Source Type@Global End Time@Global Start Time@!Full Solver Reset:SIMSCR Execution Mode.ctl@Execution Mode@! Nan/Inf Check~ SimParams.ctlh@P+tuvwxyz{|}~Timing @!Input?@!timing src wired?@0 Target Name@S Target DataZXDataNode.xnodenitl_TargetSpecificData.ctl6@PTL Target Specific Data"@@Target Specific Data@S G Only Data@ID @!Wired?@0Type@PPearl@@Size@@Hidden@ TL_Lft_Ear TL_Rt_Ear TL_Lft_DnTL_Rf_Dn TS_Lft_Ear TS_Rt_EarTS_1stFrame_Lft_Dn TS_Lft_DnTS_LastFrame_Rt_DnTS_Rt_Dn TL_TS_Lft_Ear TL_TS_Rt_Ear TL_TS_Lft_Dn TL_TS_Rt_DnTL_TS_1stFrame_Lft_DnTL_TS_LastFrame_Rt_Dn SIM_Lft_Ear SIM_Rt_Ear DataNode_Type @!Boolean@@ InvisibleB SimDog.xnode SimDog.ctl.@P State@ Runge-Kutta 1 (Euler) Runge-Kutta 2 Runge-Kutta 3 Runge-Kutta 4Runge-Kutta 23 (variable)Runge-Kutta 45 (variable)BDF (variable)Adams-Moulton (variable)Rosenbrock (variable)Discrete States Only Linearizer State Query Trim Eval ODE Solver@Execution Moded@P+tuvxyz{|}~Timing SimParams.ctlv@P+tuvwxyz{|}~Default Constant Data @' @ P @ P Runge-Kutta 1 (Euler) Runge-Kutta 2 Runge-Kutta 3 Runge-Kutta 4Runge-Kutta 23 (variable)Runge-Kutta 45 (variable)BDF (variable)Adams-Moulton (variable)Rosenbrock (variable)Discrete States Only Linearizer State Query Trim Eval @ P @PolyIdx\SIMX SubVIIconStyle.ctl<@StaticDynamic ParameterizedTextOnly Icon Style@3Icon @0IDmSIMX ParamSrcPrivate.ctlK@ Config PageInternal TerminalOnlyTerminalConfigPageOnlySource@0String@@Feedthrough Map @flags@ ConPane IdxASIMX ParamHeader.ctl#@P ParamHeader @SValue@STypeDesc9NI_XNodeSupport.lvlib XNodeInt.ctl#@Left7NI_XNodeSupport.lvlib XNodeInt.ctl!@Top9NI_XNodeSupport.lvlib XNodeInt.ctl#@Right;NI_XNodeSupport.lvlib XNodeInt.ctl%@BottomHNI_XNodeSupport.lvlibXNodeRect32.ctl0@PBoundsF BSIMX ParameterElement.ctl$@PParameter Element@@ Instances: BSIMX ParameterRec.ctl@P ParameterRec@@ Parameters @!VI Ok?@2VI Path@0 Attribute@@ AttributesMFSIMX ImplementationElement.ctl%@PCurrent Implementation@@Displayed Params@v@h3H XPoint32.ctl@PParam Minimums3H XPoint32.ctl@PParam Maximums1H XPoint32.ctl@P Param CurrentRSIMX ParameterizedIconState.ctl*@PParameterized Icon Info@@ Text Inputs@@ Text Outputs1H XPoint32.ctl@P Text Minimums1H XPoint32.ctl@P Text Maximums1H XPoint32.ctl@P Text Current@ Output WidthMMSIMX TextOnlyIconState.ctl)@PText Only Icon InfoB BSIMX SubVIState.ctl&@P SubVI Info @ColorKSIMX Orientation.ctl-@ForwardBackwardBlock OrientationQSIMX DiagramType.ctl3@SimDiagCompDiag StandardDiag Target Diag@0 DisplayName @SVarData? BSimX_Generic.ctl%@P Generic Info:SIMX Halt.xnode SIMX Halt.ctl$@PState @!Halt?@ RK 1 (Euler) Linearizer State Query Trim EvalAdamsRK 3RK 4RK 45BDFRK 2RK 23 RosenbrockDiscrete States Onlycontinuous integrator@ initial time@ final time@ step size@ proposed step size@ max step size@ min step size@ discrete time step@ max step ratio>@Init Minor Substep Major SubstepFinalDiag Eval Stage@ Substep Index@ Timestep Index@ simulation time@ current timestep base@ proposed step time@ absolute tolerance@ relative tolerance@!step accepted?@!step complete?@!reset integrator?@ machine epsilon@ min float@Perror@ Method Order@!Finished Late [i-1]@!Discrete step?@!NaN and Inf check?@ Final Timestep Index@!(maj+disc)or(init)?@!check vector sizes?@!solver handles zc?@ Current Idx @0Tag@@ Node Tags@ Input Width @Disc ID@ Num Cont St@ Cont St Idx@ Num Disc St@ Disc St Idx @P Node Header@@ Node Headers @ Signal@@ Node Data@@ Node Outputs@@ Z.C. Signals0@risingfallingeithernone trigger type @@Z.C. Trigger Types@P Node Record@@! Node Data @ Numeric@@#inputs@@#outputs@@#reset@@# lower limits@@# upper limits(@upperlowerbothnone limit type@@) limit types@@ reset types @@#initial conditions@@# reset I.C.@@limited?@@ State Names,@P $%&'(*+,-./Cont State data@ tick period (sec)@ time (ticks)@@fire?@ period (sec)@@4 period (sec)@@4 skew (sec)@ period (sec)@@7 period (tick)@@7 skew (tick)@P5689registry@!discrete blocks?@ steps per tick@ steps to tick@!discrete tick?$@P123:;<=> DiscreteInfo@@# Disc States@P@/Disc State data@Error Block ID@PBRegistry Error @Numeric@@D ZC Indices,@P "0?ACESimulation Registry@!variable step solver?@!First Substep?@!Continuous States?b@P&     FGHISimulation dataf@P&     FGHISimulation data out@millisecond multipleP++# @MPPN0O@ BSimX_SubVIWrapper.ctl"@PSubVI Wrapper Info @2Configuration CallbacksLNSIMX ConfigurableSubVIState.ctl$@PRConfigurable SubVI InfoF BSIMX Integrator.xnodeSIMX Integrator.ctl*@PQSState @ input @ output@!limited?@ initial condition? BSimX_Generic.ctl%@P Generic State@SIMX NAryIcon.ctl&@Circle Rectangle Icon Type@Operator@@[InputOps@Polymorphic Type@! Polymorphic?@@]Term DatatypesASIMX NAryState.ctl%@PZ\]^_NAryOp SimX InfoD`SIMX Summation.xnodeSIMX Summation.ctl(@PY`State @ Result@ Operand2@ Operand1NSIMX Multiplication.xnodeSIMX Multiplication.ctl.@PY`StateJSIMX TimeWaveform.xnodeSIMX TimeWaveform.ctl,@PQSState @ Value @Enum @Enum@Expected End [f-1]@Actual End [f-1]@!Finished Late? [f-1]@Expected End [i-1]@Actual End [i-1]@!Finished Late? [i-1]@Expected Start [i]@Actual Start [i]@Expected Start [f]@Actual Start [f]XDNodeRunTimeDep.lvlibnitl_modes.ctl@ No Change/Process missed periods, maintain original phase/Discard missed periods, maintain original phase-Process missed periods, ignore original phase-Discard missed periods, ignore original phaseModeXDNodeRunTimeDep.lvlib wakeup.ctl~@NormalAbortedAsynchronous wakeupTiming source errorTimed loop errorTimeout Wakeup Reason@Frame Duration@Iteration Duration@ Assigned CPUzcsXDNodeRunTimeDep.lvlibtiming_clust.ctl`@PjklmnopqrstuvwxTiming @SType@StaticIDEbXDataNode.xnode TermInfo.ctl/@Pz{TermInfo@@|Size@@|Hidden]XDataNode.xnode DN_Type.ctl@ TL_Lft_Ear TL_Rt_Ear TL_Lft_DnTL_Rt_Dn TS_Lft_Ear TS_Rt_EarTS_1stFrame_Lft_Dn TS_Lft_DnTS_LastFrame_Rt_DnTS_Rt_Dn TL_TS_Lft_Ear TL_TS_Rt_Ear TL_TS_Lft_Dn TL_TS_Rt_DnTL_TS_1stFrame_Lft_DnTL_TS_LastFrame_Rt_Dn DataNode_TypeH(XDataNode.xnode XDataNode.ctl2@P y}~StateZ@NormalAbortedAsynchronous wakeupTiming source errorTimed loop errorTimeout @ P@ No Change/Process missed periods, maintain original phase/Discard missed periods, maintain original phase-Process missed periods, ignore original phase-Discard missed periods, ignore original phase @ P@!t9 2NI_XNodeSupport.lvlib XNodeInt.ctl#@Left7 2NI_XNodeSupport.lvlib XNodeInt.ctl!@Top9 2NI_XNodeSupport.lvlib XNodeInt.ctl#@Right; 2NI_XNodeSupport.lvlib XNodeInt.ctl%@BottomH CNI_XNodeSupport.lvlibXNodeRect32.ctl0@PBoundsFYuSIMX ParameterElement.ctl$@PParameter Element@@ Instances:YuSIMX ParameterRec.ctl@P ParameterRec@@ ParametersBYuSIMX SubVIState.ctl&@P SubVI Info?YuSimX_Generic.ctl%@P Generic Info@YvSIMX Manager.xnodeSIMX Manager.ctl&@PState @O P0 P$ @ PO @!Stop?@0message @!result @) PGSIM limit type.ctl+@upperlowerbothnone limit type@ upper limit @ initial condition for reset @ reset @ POSIM trigger type.ctl1@risingfallingeithernone reset type@ lower limit"@0DNL_Simulation CallChainVNormalAbortedAsynchronous wakeupTiming source errorTimed loop errorTimeout @ P No Change/Process missed periods, maintain original phase/Discard missed periods, maintain original phase-Process missed periods, ignore original phase-Discard missed periods, ignore original phase @ P c1 c@ d( c  cc_SYVj] c0 cSIM integration method.ctl@ RK 1 (Euler) Linearizer State Query Trim EvalAdamsRK 3RK 4RK 45BDFRK 2RK 23 RosenbrockDiscrete States Onlycontinuous integratoreSIM diagram eval stage.ctlA@Init Minor Substep Major SubstepFinalDiag Eval StageI2RZSIM Registry Node Header.ctl#@P Node Header@@ Node HeadersQSIM trigger type.ctl3@risingfallingeithernone trigger type @@Z.C. Trigger TypesC:SIM Registry Node Record.ctl@P Node Record@@ Node Data@@ limit types@@ reset typesRSIM solver state data.ctl0@P $%&'(,-./Cont State dataFcASIM discrete data.ctl(@P123:;<=> DiscreteInfoBSIM Discrete state data.ctl@P@/Disc State dataH2Q!SIM Simulation Registry Error.ctl@PBRegistry ErrorTlWSIM Simulation Registry.ctl0@P ESimulation RegistrynSIM simulation data.ctlj@P&     GHISimulation data Out@P error out cnSIM simulation data.ctlj@P&     GHISimulation data outSIM integration method.ctl} RK 1 (Euler) Linearizer State Query Trim EvalAdamsRK 3RK 4RK 45BDFRK 2RK 23 RosenbrockDiscrete States Only"@Default Collector Stop Mode c SimParams.ctlv@P+tuvwxyz{|}~SimulationParameters@ number: 0 to 1@ Initial Time@ Final Time@ Time Step@ Runge-Kutta 1 (Euler) Runge-Kutta 2 Runge-Kutta 3 Runge-Kutta 4Runge-Kutta 23 (variable)Runge-Kutta 45 (variable)BDF (variable)Adams-Moulton (variable)Rosenbrock (variable)Discrete States Only Linearizer State Query Trim EvalContinuous Solver Method@ Minimum Time Step@ Maximum Time Step@ Initial Time Step@!AutoFixedStepSize@!AutoDiscreteStepSize@ Discrete Time Step"@!CalculatePeriodUsingTimeStep@! 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Trigger TypesC:SIM Registry Node Record.ctl@P Node Record@@ Node DataGSIM limit type.ctl+@upperlowerbothnone limit type@@ limit types@@ reset typesRSIM solver state data.ctl0@P   Cont State dataFcASIM discrete data.ctl(@P DiscreteInfoBSIM Discrete state data.ctl@PDisc State dataH2Q!SIM Simulation Registry Error.ctl@P'Registry ErrorTlWSIM Simulation Registry.ctl0@P   Simulation RegistrynSIM simulation data.ctlf@P&wxyz{|}~2VWSimulation datanSIM simulation data.ctlj@P&wxyz{|}~2VWSimulation data outLmmmmmmm2mmmmmm @millisecond timer value@millisecond multiple @Enum@ BSimX_SubVIWrapper.ctl"@PSubVI Wrapper Info @2Configuration CallbacksLNSIMX ConfigurableSubVIState.ctl$@PConfigurable SubVI InfoF BSIMX Integrator.xnodeSIMX Integrator.ctl*@PState@!limited? @ output @ input@!Switch_filling? @Enum@ upper limit @ initial condition for reset@ initial condition @ resetOSIM trigger type.ctl1@risingfallingeithernone reset type@ lower limitLm  mm!m"#$%mm @ Result @ h0 [m]@ Operand2? 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Valve_out @ A [m2]@ Block Idx OutL  mmmm"mm%;T  "risingfallingeithernoneupperlowerbothnonenSIM simulation data.ctlj@P&wxyz{|}~2VWSimulation data Out SimParams.ctlv@P+345678 9:;<=>?@ABCDEFGHIJKLMNOP$Q)RSTUVW0Simulation Params out@P&'(error in<_Q @ number: 0 to 1@P&'( error out@P&'(error 2@P&'(error 1,]mmmmm^_`  @!result"@Default Collector Stop Mode,mmaXmmb`  P] @!Stop?nSIM simulation data.ctlj@P&wxyz{|}~2VWSimulation data inemf( @0message@0button name ("OK") @!trueem( SIM integration method.ctl} RK 1 (Euler) Linearizer State Query Trim EvalAdamsRK 3RK 4RK 45BDFRK 2RK 23 RosenbrockDiscrete States Only9 2NI_XNodeSupport.lvlib XNodeInt.ctl#@Left7 2NI_XNodeSupport.lvlib XNodeInt.ctl!@Top9 2NI_XNodeSupport.lvlib XNodeInt.ctl#@Right; 2NI_XNodeSupport.lvlib XNodeInt.ctl%@BottomH CNI_XNodeSupport.lvlibXNodeRect32.ctl0@PmnopBoundsFYuSIMX ParameterElement.ctl$@PqParameter Element@@r Instances:YuSIMX ParameterRec.ctl@Ps ParameterRec@@t ParametersBYuSIMX SubVIState.ctl&@Pu SubVI Info?YuSimX_Generic.ctl%@Pq Generic Info@YvSIMX Manager.xnodeSIMX Manager.ctl&@PvwStatem(   SimParams.ctlz@P+345678 9:;<=>?@ABCDEFGHIJKLMNOP$Q)RSTUVW0SimulationParameters out SimParams.ctlv@P+345678 9:;<=>?@ABCDEFGHIJKLMNOP$Q)RSTUVW0SimulationParameters,mzmmm{m`  SimParams.ctlz@P+345678 9:;<=>?@ABCDEFGHIJKLMNOP$Q)RSTUVW0SimulationParameters Out@!First Call?: T/F@Expected End [f-1]@Actual End [f-1]@!Finished Late? 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[i-1]@Expected Start [i]@Actual Start [i]@Expected Start [f]@Actual Start [f]XDNodeRunTimeDep.lvlibnitl_modes.ctl@ No Change/Process missed periods, maintain original phase/Discard missed periods, maintain original phase-Process missed periods, ignore original phase-Discard missed periods, ignore original phaseModeXDNodeRunTimeDep.lvlib wakeup.ctl~@NormalAbortedAsynchronous wakeupTiming source errorTimed loop errorTimeout Wakeup Reason@Frame Duration@Iteration Duration@ Assigned CPUzcsXDNodeRunTimeDep.lvlibtiming_clust.ctl`@PIJKLMNOP)RSTUTiming @SType@StaticIDEbXDataNode.xnode TermInfo.ctl/@P`aJYTermInfo@@Size@@Hidden]XDataNode.xnode DN_Type.ctl@ TL_Lft_Ear TL_Rt_Ear TL_Lft_DnTL_Rt_Dn TS_Lft_Ear TS_Rt_EarTS_1stFrame_Lft_Dn TS_Lft_DnTS_LastFrame_Rt_DnTS_Rt_Dn TL_TS_Lft_Ear TL_TS_Rt_Ear TL_TS_Lft_Dn TL_TS_Rt_DnTL_TS_1stFrame_Lft_DnTL_TS_LastFrame_Rt_Dn DataNode_TypeH(XDataNode.xnode XDataNode.ctl2@P hYZ^_State@ No Change/Process missed periods, maintain original phase/Discard missed periods, maintain original phase-Process missed periods, ignore original phase-Discard missed periods, ignore original phase Z@NormalAbortedAsynchronous wakeupTiming source errorTimed loop errorTimeout B@PIJKLMNOP)RSTU >PIJKLMNOP)RSTU@!t>P@@CC)@@m No Change/Process missed periods, maintain original phase/Discard missed periods, maintain original phase-Process missed periods, ignore original phase-Discard missed periods, ignore original phaseVNormalAbortedAsynchronous wakeupTiming source errorTimed loop errorTimeout]Z L{mm)ImKmOmMmm}mP  SimParams.ctlv@P+345678 9:;<=>?@ABCDEFGHIJKLMNOP$Q)RSTUVW0Simulation Params in< mmmYmmmmmZmx  121iil)l)mmmmmmmnmmm345o678 9:;<=>?@ABCDEFGHIJKLMNOP$Q&'()RSTUVpW0qrrTSR)Q$PONMLKJIHGFEDCBA@?>=<;:9 87j543lstmmXmmmmmmmummmmmmm2mmmmmmm  mm!m"#$%mm&"'((')2)34566789<m;% #m!mmm: ==6==7577533)>?434BCA@ECD@J?K?mmKmmm?mLMN4NNO$PPQQQRRRSSUT;%mmN888OONPN"mmmm  92mmmmm%%$$V##!!    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